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mcm69p818 1 motorola fast sram 256k x 18 bit pipelined burstram synchronous fast static ram the mcm69p818 is a 4m bit synchronous fast static ram designed to provide a burstable, high performance, secondary cache for the powerpc ? and other high performance microprocessors. it is organized as 256k words of 18 bits each. this device integrates input registers, an output register, a 2bit address counter, and a high speed sram onto a single monolithic circuit for reduced parts count in cache data ram applications. synchronous design allows precise cycle control with the use of an external clock (k). addresses (sa), data inputs (dqx), and all control signals except output enable (g ) and linear burst order (lbo ) are clock (k) controlled through positive edgetriggered noninverting registers. bursts can be initiated with either adsp or adsc input pins. subsequent burst addresses can be generated internally by the mcm69p818 (burst sequence operates in linear or interleaved mode dependent upon the state of lbo ) and controlled by the burst address advance (adv ) input pin. write cycles are internally selftimed and are initiated by the rising edge of the clock (k) input. this feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. synchronous byte write (sbx ), synchronous global write (sgw ), and synchro- nous write enable (sw ) are provided to allow writes to either individual bytes or to all bytes. the two bytes are designated as aao and abo. sba controls dqa and sbb controls dqb. individual bytes are written if the selected byte writes sbx are asserted with sw . all bytes are written if either sgw is asserted or if all sbx and sw are asserted. for read cycles, pipelined srams output data is temporarily stored by an edgetriggered output register and then released to the output buffers at the next rising edge of clock (k). the mcm69p818 operates from a 3.3 v core power supply and all outputs operate on a 2.5 v or 3.3 v power supply. all inputs and outputs are jedec stan- dard jesd85 compatible. ? mcm69p8183.5: 3.5 ns access/6 ns cycle (166 mhz) mcm69p8183.8: 3.8 ns access/6.7 ns cycle (150 mhz) mcm69p8184: 4 ns access/7.5 ns cycle (133 mhz) ? 3.3 v + 10%, 5% core power supply, 2.5 v or 3.3 v i/o supply ? adsp , adsc , and adv burst control pins ? selectable burst sequencing order (linear/interleaved) ? 2cycle deselect timing ? internally selftimed write cycle ? byte write and global write control ? pb1 version 2.0 compatible ? jedec standard 119pin pbga package the powerpc name is a trademark of ibm corp., used under license therefrom. order this document by mcm69p818/d semiconductor technical data mcm69p818 zp package pbga case 99902 rev 2 11/7/97 ? motorola, inc. 1997
mcm69p818 2 motorola fast sram write register a enable register burst counter adsp g clr write register b sba sbb se3 16 18 sgw dataout register enable register k2 k address register 18 datain register 256k x 18 array se2 lbo adv k adsc sa sa1 sa0 sw se1 k 2 18 2 2 k2 dqa dqb 18 functional block diagram
mcm69p818 3 motorola fast sram top view 119 bump pbga 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss v ss v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa sa sa sa sa nc nc nc sa sa nc nc sw nc nc v ddq v ddq nc v ddq dqa dqa dqa dqa nc v dd nc nc nc nc nc nc nc dqb v ss sa0 nc lbo nc dqa sa1 v ss nc dqb v ddq dqb v ss nc nc dqa sba v ss nc dqb nc dqb v ss kv ss dqb nc v dd nc v dd nc v dd v ddq nc v ss sgw dqa dqa nc adv sbb dqb nc v ddq nc v ss g nc se1 v ss dqb nc dqb nc v ss nc dqa v dd nc nc se2 sa adsc adsp k l m n p r t u not to scale v ddq v ddq se3 v ddq v ddq nc pin assignment
mcm69p818 4 motorola fast sram pbga pin descriptions pin locations symbol type description 4b adsc input synchronous address status controller: active low, interrupts any ongoing burst and latches a new external address. used to initiate a read, write, or chip deselect. 4a adsp input synchronous address status processor: active low, interrupts any ongoing burst and latches a new external address. used to initiate a new read, write, or chip deselect (exception e chip deselect does not occur when adsp is asserted and se1 is high). 4g adv input synchronous address advance: increments address count in accordance with counter type selected (linear/interleaved). (a) 6d, 7e, 6f, 7g, 6h, 7k, 6l, 6n, 7p (b) 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b). 4f g input asynchronous output enable input: low e enables output buffers (dqx pins). high e dqx pins are high impedance. 4k k input clock: this signal registers the address, data in, and all control signals except g and lbo . 3r lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter (68k/powerpc). high e interleaved burst counter (486/i960/pentium). 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 2r, 6r, 2t, 3t, 5t, 6t sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 4n, 4p sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 5l, 3g (a) (b) sbx input synchronous byte write inputs: axo refers to the byte being written (byte a, b). sgw overrides sbx . 4e se1 input synchronous chip enable: active low to enable chip. negated high e blocks adsp or deselects chip when adsc is asserted. 2b se2 input synchronous chip enable: active high for depth expansion. 6b se3 input synchronous chip enable: active low for depth expansion. 4h sgw input synchronous global write: this signal writes all bytes regardless of the status of the sbx and sw signals. if only byte write signals sbx are being used, tie this pin high. 4m sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. if only byte write signals sbx are being used, tie this pin low. 4c, 2j, 4j, 6j, 4r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply i/o power supply. 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p v ss supply ground. 1b, 7b, 1c, 7c, 2d, 4d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 3j, 5j, 1k, 6k, 2l, 4l, 7l, 6m, 2n, 7n, 1p, 6p, 1r, 5r, 7r, 1t, 4t, 7t, 2u, 3u, 4u, 5u, 6u nc e no connection: there is no connection to the chip.
mcm69p818 5 motorola fast sram truth table (see notes 1 through 5) next cycle address used se1 se2 se3 adsp adsc adv g 3 dqx write 2, 4 deselect none 1 x x x 0 x x highz x deselect none 0 x 1 0 x x x highz x deselect none 0 0 x 0 x x x highz x deselect none x x 1 1 0 x x highz x deselect none x 0 x 1 0 x x highz x begin read external 0 1 0 0 x x x highz x 5 begin read external 0 1 0 1 0 x x highz read 5 continue read next x x x 1 1 0 1 highz read continue read next x x x 1 1 0 0 dq read continue read next 1 x x x 1 0 1 highz read continue read next 1 x x x 1 0 0 dq read suspend read current x x x 1 1 1 1 highz read suspend read current x x x 1 1 1 0 dq read suspend read current 1 x x x 1 1 1 highz read suspend read current 1 x x x 1 1 0 dq read begin write external 0 1 0 1 0 x x highz write continue write next x x x 1 1 0 x highz write continue write next 1 x x x 1 0 x highz write suspend write current x x x 1 1 1 x highz write suspend write current 1 x x x 1 1 x highz write notes: 1. x = don't care. 1 = logic high. 0 = logic low. 2. write is defined as either (a) any sbx and sw low or (b) sgw is low. 3. g is an asynchronous signal and is not sampled by the clock k. g drives the bus immediately (t glqx ) following g going low. 4. on write cycles that follow read cycles, g must be negated prior to the start of the write cycle to ensure proper write data setup times. g must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. this read assumes the ram was previously deselected. linear burst address table (lbo = v ss ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (lbo = v dd ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00 write truth table cycle type sgw sw sba sbb read h h x x read h l h h write byte a h l l h write byte b h l h l write all bytes h l l l write all bytes l x x x
mcm69p818 6 motorola fast sram absolute maximum ratings (see note 1) rating symbol value unit notes power supply voltage v dd v ss 0.5 to + 4.6 v i/o supply voltage v ddq v ss 0.5 to v dd v 2 input voltage relative to v ss for any pin except v dd v in , v out v ss 0.5 to v dd + 0.5 v 2 input voltage (threestate i/o) v it v ss 0.5 to v ddq + 0.5 v 2 output current (per i/o) i out 20 ma package power dissipation p d 1.6 w 3 ambient temperature t a 0 to 70 c die temperature t j 110 c 3 temperature under bias t bias 10 to 85 c storage temperature t stg 55 to 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. this is a steadystate dc parameter that is in effect after the power supply has achieved its nominal operating level. power sequencing can not be controlled and is not allowed. 3. power dissipation capability is dependent upon package characteristics and use environment. see package thermal characteristics. package thermal characteristics e pbga rating symbol max unit notes junction to ambient (@ 200 lfm) single layer board four layer board r q ja 41 19 c/w 1, 2 junction to board (bottom) r q jb 11 c/w 3 junction to case (top) r q jc 9 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface via the cold plate method (mil spec883 method 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit.
mcm69p818 7 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t a = 0 to 70 c, unless otherwise noted) recommended operating conditions: 2.5 v i/o supply (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 2.9 v input low voltage v il 0.3 e 0.7 v input high voltage v ih 1.7 e v dd + 0.3 v input high voltage (i/o pins) v ih2 1.7 e v ddq + 0.3 v recommended operating conditions: 3.3 v i/o supply (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 3.135 3.3 v dd v input low voltage v il 0.5 e 0.8 v input high voltage v ih 2 e v dd + 0.5 v input high voltage (i/o pins) v ih2 2 e v ddq + 0.5 v v ih 20% t khkh (min) v ss v ss 1.0 v figure 1. undershoot voltage
mcm69p818 8 motorola fast sram dc characteristics and supply currents parameter symbol min typ max unit notes input leakage current (0 v v in v dd ) i lkg (i) e e 1 m a output leakage current (0 v v in v dd ) i lkg (o) e e 1 m a ac supply current (device selected, mcm69p8183.5 all outputs open, freq = max) mcm69p818 3.8 i dda e e e e 425 4 00 ma 1, 2, 3 all outputs open , freq = max) mcm69p818 3 . 8 includes v dd only mcm69p8184 e e e e 400 375 cmos standby supply current (device deselected, freq = 0, v dd = max, all inputs static at cmos levels) i sb2 e e 45 ma 4, 5 ttl standby supply current (device deselected, freq = 0, v dd = max, all inputs static at ttl levels) i sb3 e e 50 ma 4, 6 clock running (device deselected, mcm69p8183.5 freq = max, v dd = max, mcm69p818 3.8 i sb4 e e e e 190 180 ma 4, 5 freq = max , v dd = max , mcm69p818 3 . 8 all inputs toggling at cmos levels) mcm69p8184 e e e e 180 165 static clock running (device deselected, freq = max, v dd = max, all inputs static at ttl levels) i sb5 e e 95 ma 4, 6 output low voltage (i ol = 2 ma), v ddq = 2.5 v v ol e e 0.7 v output high voltage (i oh = 2 ma), v ddq = 2.5 v v oh 1.7 e e v output low voltage (i ol = 8 ma), v ddq = 3.3 v v ol2 e e 0.4 v output high voltage (i oh = 4 ma), v ddq = 3.3 v v oh2 2.4 e e v notes: 1. reference ac operating conditions and characteristics for input and timing. 2. all addresses transition simultaneously low (lsb) and then high (msb). 3. data states are all zero. 4. device in deselected mode as defined by the truth table. 5. cmos levels for i/o's are v it v ss + 0.2 v or v ddq 0.2 v. cmos levels for other inputs are v in v ss + 0.2 v or v dd 0.2 v. 6. ttl levels for i/o's are v it v il or v ih2 . ttl levels for other inputs are v in v il or v ih . capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 0 to 70 c, periodically sampled rather than 100% tested) parameter symbol min typ max unit input capacitance c in e 4 5 pf input/output capacitance c i/o e 7 8 pf
mcm69p818 9 motorola fast sram ac operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t a = 0 to 70 c, unless otherwise noted) input timing measurement reference level 1.25 v . . . . . . . . . . . . . . input pulse levels 0 to 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall times 1.0 v/ns (20 to 80%) . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.25 v . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 2 unless otherwise noted . . . . . . . . . . . . . . read/write cycle timing (see notes 1 and 2) p sbl mcm69p8183.5 166 mhz mcm69p8183.8 150 mhz mcm69p8184 133 mhz ui n parameter symbol min max min max min max unit notes cycle time t khkh 6 e 6.7 e 7.5 e ns clock high pulse width t khkl 2.4 e 2.6 e 3 e ns 3 clock low pulse width t klkh 2.4 e 2.6 e 3 e ns 3 clock access time t khqv e 3.5 e 3.8 e 4 ns output enable to output valid t glqv e 3.5 e 3.5 e 3.8 ns clock high to output active t khqx1 0 e 0 e 0 e ns 4, 5 clock high to output change t khqx2 1.5 e 1.5 e 1.5 e ns 4 output enable to output active t glqx 0 e 0 e 0 e ns 4, 5 output disable to q highz t ghqz e 3.5 e 3.5 e 3.8 ns 4, 5 clock high to q highz t khqz 1.5 6 1.5 6.7 1.5 7.5 ns 4, 5 setup times: address adsp , adsc , adv data in write chip enable t adkh t adskh t dvkh t wvkh t evkh 1.5 e 1.5 e 1.5 e ns hold times: address adsp , adsc , adv data in write chip enable t khax t khadsx t khdx t khwx t khex 0.5 e 0.5 e 0.5 e ns notes: 1. write is defined as either any sbx and sw low or sgw is low. chip enable is defined as se1 low, se2 high, and se3 low whenever adsp or adsc is asserted. 2. all read and write cycle timings are referenced from k or g . 3. in order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, fsram ac parametric specifications are always specified at v ddq /2. in some design exercises, it is desirable to evaluate timing using other reference levels. since the maximum test input edge rate is known and is given in the ac test conditions section of the data sheet as 1 v/ns, one can easily interpolate timing values to other reference levels. 4. this parameter is sampled and not 100% tested. 5. measured at 200 mv from steady state. output z 0 = 50 w r l = 50 w 1.25 v figure 2. ac test load
mcm69p818 10 motorola fast sram figure 3. lumped capacitive load and typical derating curve 5 4 3 2 1 0 lumped capacitance, c l (pf) 100 80 60 40 20 0 c l clock access time delay (ns) output 2.0 input waveform t r test point output buffer 2.0 0.5 0.5 output waveform output load t f unloaded rise and fall time measurement notes: 1. input waveform has a slew rate of 1 v/ns. 2. rise time is measured from 0.5 to 2.0 v unloaded. 3. fall time is measured from 2.0 to 0.5 v unloaded. figure 4. unloaded rise and fall time characterization 2.0 0.5 2.0 0.5
mcm69p818 11 motorola fast sram (a) pullup for 2.5 v i/o supply (c) pulldown voltage (v) pullup i (ma) min i (ma) max 0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 38 38 38 26 20 0 0 0 105 105 105 83 70 30 10 0 voltage (v) pulldown i (ma) min i (ma) max 0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 0 0 10 20 31 40 40 40 40 0 0 20 40 63 80 80 80 80 figure 5. typical output buffer characteristics 2.9 2.5 2.3 2.1 1.25 0.8 0 0 38 105 current (ma) voltage (v) v dd 1.6 1.25 0.3 0 040 80 current (ma) voltage (v) (b) pullup for 3.3 v i/o supply voltage (v) pullup i (ma) min i (ma) max 0.5 0 1.4 1.65 2.0 3.135 3.6 50 50 50 46 35 0 0 150 150 150 130 101 25 0 3.135 2.8 1.65 1.4 0 0 50 current (ma) voltage (v) 3.6 150 100 3.6 46 120
mcm69p818 12 motorola fast sram burst read single read adsc t khkl t khkh dqx e k adsp adv q(a) q(n) burst write adsp, sa sa ab read/write cycles t klkh cd se1 w q(b) q(b+1) t khqv burst wraps around q(b+2) q(b+3) q(b) d(c) d(c+1) d(c+2) d(c+3) q(d) t khqv deselected single read se2, se3 ignored g t khqz t khqx2 t ghqz t glqx note: e low = se2 high and se3 low. w low = sgw low and/or sw and sbx low. t khqx1
mcm69p818 13 motorola fast sram application information stop clock operation in the stop clock mode of operation, the sram will hold all state and data values even though the clock is not running (full static operation). the sram design allows the clock to start with adsp and adsc , and stops the clock after the last write data is latched, or the last read data is driven out. when starting and stopping the clock, the ac clock timing and parametrics must be strictly maintained. for example, clock pulse width and edge rates must be guaranteed when starting and stopping the clocks. to achieve the lowest power operation for all three stop clock modes, stop read, stop write, and stop deselect: ? force the clock to a low state. ? force the control signals to an inactive state (this guaran- tees any potential source of noise on the clock input will not start an unplanned on activity). ? force the address inputs to a low state. k adsp address adv a1 a2 q(a1+1) q(a2) q(a1) adsp (initiates burst read) clock stop (continue burst read) wake up adsp (initiates burst read) note: for lowest possible power consumption during stop clock, the addresses should be driven to a low state (v il ). best results are obtained if v il < 0.2 v. dqx stop clock with read timing
mcm69p818 14 motorola fast sram k adsc address write a1 a2 adsc (initiates burst write) clock stop (continue burst write) wake up adsc (initiates burst write) d(a1) data in d(a1+1) d(a2) dqx highz adv v ih or v il fixed (see note) note: while the clock is stopped, data in must be fixed in a high (v ih ) or low (v il ) state to reduce the dc current of the input buffers. for lowest power operation, all data and address lines should be held in a low (v il ) state and control lines held in an inactive state. stop clock with write timing
mcm69p818 15 motorola fast sram nonburst synchronous operation although this burstram has been designed for powerpc based and other high end mpubased systems, these srams can be used in other high speed l2 cache or memory applications that do not require the burst address feature. most l2 caches designed with a synchronous inter- face can make use of the mcm69p818. the burst counter feature of the burstram can be disabled, and the sram can be configured to act upon a continuous stream of addresses. see figure 6. control pin tie values (h v ih , l v il ) nonburst adsp adsc adv se1 lbo sync nonburst, pipelined sram h l h l x note: although x is specified in the table as a don't care, the pin must be tied either high or low. writes reads q(b) q(a) ab cd ef gh w q(d) q(c) d(f) d(e) d(h) d(g) g figure 6. configured as nonburst synchronous sram dq addr k mcm 69p818 xx x x motorola memory prefix part number full part numbers e mcm69p818zp3.5 mcm69p818zp3.8 mcm69p818zp4 mcm69p818zp3.5r mcm69p818zp3.8r mcm69p818zp4r package (zp = pbga) blank = trays, r = tape and reel speed (3.5 = 3.5 ns, 3.8 = 3.8 ns, 4 = 4.0 ns) ordering information (order by full part number)
mcm69p818 16 motorola fast sram zp package 7 x 17 bump pbga case 99902 package dimensions a b c d e f g h j k l m n p r t u d2 e2 4x 16x 119x top view bottom view side view d 0.20 6x e e 7654321 b 0.35 a c e 0.25 a 0.20 a a seating plane a a1 a2 a3 m 0.3 c a b m 0.15 a d1 e1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. all dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. dim min max millimeters a 2.40 a1 0.50 0.70 a2 1.30 1.70 a3 0.80 1.00 d 22.00 bsc d1 20.32 bsc d2 19.40 19.60 e 14.00 bsc e1 7.62 bsc e2 11.90 12.10 b 0.60 0.90 e 1.27 bsc b motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan: nippon motorola ltd.; spd, strategic planning office; 4-32-1, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 nishi-gotanda; shinagawa-ku, tokyo 141, japan. 81-3-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & c anada only 1-800-774-1848 51 ting kok road, tai po, n.t., hong kong. 852-26629298 http ://sps.motorola.com /mfax / home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm69p818/d ?

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